Charge pump voltage doubler circuits are a building block of integrated circuits providing an output voltage higher than the power supply voltage. The trend for lower power supply voltages at the input of integrated circuits (e.g. in the context of single battery operation) and the trend for flexible operating conditions (e.g. in the context of wide input power supply range integrated circuits) are resulting in more applications for charge pump voltage doublers and creates the need for new design topologies performing with relatively low input voltages and with increased power efficiency.
Charge pump voltage doublers may require two boosting capacitors per doubling stage. Furthermore, charge pump voltage doublers may only be operable for input voltages which are substantially higher than the threshold voltage of transistors comprised within the voltage doublers. In addition, charge pump voltage doublers may make use of triple well CMOS (Complementary metal oxide semiconductor) technology, thereby increasing the cost of the voltage doubler. Furthermore, charge pump voltage doublers may suffer from substantial power losses.
The present document addresses the above mentioned technical problems. In particular, the present document describes a charge pump voltage doubler topology with high power efficiency, which uses only a single boosting capacitor per doubler stage and which may operate with relatively low input supply voltages. The charge pump voltage doubler which is described in the present document may be implemented using a standard CMOS process, without the need of using the relatively cost intensive triple well CMOS process.